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A Flexible and Energy-Efficient Accelerator for Graph Convolutional Neural Networks
Researchers at GW have invented a flexible and energy-efficient accelerator for graph convolutional neural networks (GCN). First, the novel accelerator design disclosed shows highly enhanced performance in comparison to existing accelerators. For example, the accelerator is capable of simultaneously improving resource utilization and data movement in...
Published: 1/7/2022
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Updated: 12/17/2021
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Inventor(s): Ahmed Louri, Jiajun Li
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture
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An Algorithm-Hardware Co-design Method for Convolutional Neural Networks
Researchers at GW have developed an algorithm-hardware co-design framework for Convolutional Neural Networks (CNN) directed towards mitigating the effects of computational irregularities in existing models. The framework disclosed allows for a reduced model size as to the associated system. For example, the algorithm disclosed utilizes centrosymmetric...
Published: 1/7/2022
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Updated: 12/17/2021
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Inventor(s): Jiajun Li, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Artificial Intelligence
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EZ-PASS: An Energy & Performance-Efficient Power-gating Router Architecture for Scalable NoCs
Researchers at The George Washington University are developing an innovative method to design a performance and power-efficient network-on-chip for the parallel computing chips. The novel network-on-chip design invented at GW will significantly improve performance and power efficiency of parallel computing chips. Considering that the innovation can...
Published: 1/7/2022
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Updated: 10/6/2021
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Inventor(s): Hao Zheng, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software > Processing Chips, Technology Classifications > Computers Electronics & Software > Computing Architecture
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Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework
Researchers at the George Washington University have invented a novel network-on-chip framework, named TSA-NoC, which significantly improves on-chip security. The invented framework also minimizes the latency and cost of security techniques for simultaneously improving system-level performance and power.
As the market for parallel computing is growing...
Published: 1/7/2022
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Updated: 10/1/2021
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Inventor(s): Ke Wang, Hao Zheng, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
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Network Design for Chiplet-based Manycore Architecture
Researchers at The George Washington University are developing a flexible interconnection network design, called Adapt-Net, for chiplet-based manycore architectures. The goal of Adapt-Net is to support the concurrent communication of diverse applications running at the same time, improving the energy-efficiency and performance of the manycore architecture....
Published: 1/7/2022
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Updated: 10/1/2021
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Inventor(s): Hao Zheng, Ke Wang, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Computing Architecture
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An Approximate Communication Framework for Network-on-chips
Reasearchers at GWU have developed an approximate communication framework for network-on-chips (NoCs), which significantly reduces the latency and power consumption of on-chip data movement. The invented framework leverages the fact that big data applications (e.g., recognition, mining, and synthesis) can tolerate modest error and transfers data with...
Published: 1/7/2022
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Updated: 9/28/2021
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Inventor(s): Ahmed Louri, Yuechen Chen
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
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