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EZ-PASS: An Energy & Performance-Efficient Power-gating Router Architecture for Scalable NoCs
Researchers at The George Washington University are developing an innovative method to design a performance and power-efficient network-on-chip for the parallel computing chips. The novel network-on-chip design invented at GW will significantly improve performance and power efficiency of parallel computing chips. Considering that the innovation can...
Published: 1/7/2022
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Updated: 10/6/2021
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Inventor(s): Hao Zheng, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software > Processing Chips, Technology Classifications > Computers Electronics & Software > Computing Architecture
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Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework
Researchers at the George Washington University have invented a novel network-on-chip framework, named TSA-NoC, which significantly improves on-chip security. The invented framework also minimizes the latency and cost of security techniques for simultaneously improving system-level performance and power.
As the market for parallel computing is growing...
Published: 1/7/2022
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Updated: 10/1/2021
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Inventor(s): Ke Wang, Hao Zheng, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
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Network Design for Chiplet-based Manycore Architecture
Researchers at The George Washington University are developing a flexible interconnection network design, called Adapt-Net, for chiplet-based manycore architectures. The goal of Adapt-Net is to support the concurrent communication of diverse applications running at the same time, improving the energy-efficiency and performance of the manycore architecture....
Published: 1/7/2022
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Updated: 10/1/2021
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Inventor(s): Hao Zheng, Ke Wang, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Computing Architecture
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